FPGA

Modélisation et accélération de réseaux de neurones profonds (CNN) en Python/VHDL/C++ et leur vérification et test à l’aide de l’environnement Pynq sur les FPGA Xilinx

S Jovanović, Serge Weber

An FPGA-based residual recurrent neural network for real-time video super-resolution

Kaicong Sun, Maurice Koch, Zhe Wang, Slavisa Jovanovic, Hassan Rabah, Sven Simon

Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks

Nicolas Marques, Hassan Rabah, Slavisa Jovanovic, Eric Dabellani, Serge Weber

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

Slavissa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda

Architecture reconfigurable de système embarqué auto-organisé

Slavisa Jovanovic

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

S Jovanović, Camel Tanougast, Christophe Bobda, Serge Weber

A new high-performance scalable dynamic interconnection for fpga-based reconfigurable systems

Slavisa Jovanovic, Camel Tanougast, Serge Weber